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Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations

François Leduc-Primeau 1, 2 Frank Kschischang Warren Gross 3
1 IMT Atlantique - ELEC - Département Electronique
2 Lab-STICC_IMTA_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 McGill University = Université McGill [Montréal, Canada]
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https://hal-imt-atlantique.archives-ouvertes.fr/hal-01779767
Contributor : François Leduc-Primeau <>
Submitted on : Thursday, April 26, 2018 - 9:16:52 PM
Last modification on : Wednesday, January 6, 2021 - 3:36:44 PM

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CNRS | INSTITUT-TELECOM | ENIB | LAB-STICC | UNIV-BREST | IMT-ATLANTIQUE

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François Leduc-Primeau, Frank Kschischang, Warren Gross. Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations. IEEE Transactions on Communications, Institute of Electrical and Electronics Engineers, 2018, 66 (3), pp.932 - 946. ⟨10.1109/TCOMM.2017.2778247⟩. ⟨hal-01779767⟩

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