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Networked Power-Gated MRAMs for Memory-Based Computing

Jean-Philippe Diguet 1 Naoya Onizawa 2 Mostafa Rizk 3, 4, 5, 6 Johanna Sepúlveda 7 Amer Baghdadi 8, 4 Takahiro Hanyu 2
1 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
4 Lab-STICC_IMTA_CACS_IAS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
6 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : Emerging non-volatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient ar- chitecture that relies on power-gated distributed Magnetoresistive Random-Access Memory (MRAM). The proposed architecture uses a Network-on-Chip (NoC) to interconnect MRAM-based clusters, processing elements, and managers. The NoC distributes application-specific commands to MRAM devices by means of packets. Configurable Network Interfaces (NI) allow to transform MRAM devices into smart units able to respond to incoming commands. In this context, three types of MRAM designs are proposed with different power-gating policies and granularities. A relevant database search engine case study is considered to illus- trate the benefits of this proposed architecture. It is implemented with a Sparse-Neural-Network (SNN) approach and simulated in SystemC with different scenarios including hundreds of database queries. Hardware designs and accurate power estimations have been conducted. The obtained results demonstrate important power reduction with database hit rates of about 94%. Targeting 65nm technology, energy savings reach 87% when compared with an SRAM-based implementation. Moreover, a new asymmetric read/write MRAM type provides from 39% to 50% energy reduction with respect to the other fixed-granularity models. This results in a low-power, highly scalable and configurable implementation of memory-based computing.
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Submitted on : Friday, September 21, 2018 - 12:45:10 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:46 PM
Long-term archiving on: : Saturday, December 22, 2018 - 2:32:22 PM

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Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Johanna Sepúlveda, Amer Baghdadi, et al.. Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2018, 26 (12), pp.1 - 13. ⟨10.1109/TVLSI.2018.2856458⟩. ⟨hal-01869484⟩

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