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A Deeply Pipelined, Highly Parallel and Flexible LDPC Decoder

Jérémy Nadal 1 Mickaël Fiorentino Elsa Dupraz 2, 3 François Leduc-Primeau 1
3 Lab-STICC_TB_CACS_COM
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
Abstract : A deeply pipelined and parallel LDPC decoder architecture is proposed in this paper. The main feature of this architecture is the ∆-update scheme, which relaxes the data dependency requirement and allows for deeper pipelines than typical decoders. The proposed architecture also has the flexibility to handle a large number of codes. Frame error rate performance is shown for three codes with different quantization parameters. Finally, the impact of pipeline depth on processing time and on the energy-delay product (EDP) is evaluated from post-synthesis results. The results show that the ability to have deeper pipelines can lead to large reductions in EDP.
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Submitted on : Friday, August 28, 2020 - 4:39:06 PM
Last modification on : Wednesday, September 2, 2020 - 3:06:36 AM

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Jérémy Nadal, Mickaël Fiorentino, Elsa Dupraz, François Leduc-Primeau. A Deeply Pipelined, Highly Parallel and Flexible LDPC Decoder. Newcas 2020, Jun 2020, Montreal, Canada. ⟨10.1109/NEWCAS49341.2020.9159808⟩. ⟨hal-02925057⟩

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