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A Deeply Pipelined, Highly Parallel and Flexible LDPC Decoder
Abstract : A deeply pipelined and parallel LDPC decoder architecture is proposed in this paper. The main feature of this architecture is the ∆-update scheme, which relaxes the data dependency requirement and allows for deeper pipelines than typical decoders. The proposed architecture also has the flexibility to handle a large number of codes. Frame error rate performance is shown for three codes with different quantization parameters. Finally, the impact of pipeline depth on processing time and on the energy-delay product (EDP) is evaluated from post-synthesis results. The results show that the ability to have deeper pipelines can lead to large reductions in EDP.
Cited literature [8 references]
https://hal-imt-atlantique.archives-ouvertes.fr/hal-02925057
Contributor : Elsa Dupraz <>
Submitted on : Friday, August 28, 2020 - 4:39:06 PM
Last modification on : Wednesday, September 2, 2020 - 3:06:36 AM
Contributor : Elsa Dupraz <>
Submitted on : Friday, August 28, 2020 - 4:39:06 PM
Last modification on : Wednesday, September 2, 2020 - 3:06:36 AM
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Nadal20Newcas.pdf
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